1. Field of the Invention
This invention relates to a method of making semiconductor device, especially with metal bumps.
2. Prior Art
In recent years, fabrication method of a semiconductor device wherein metal bumps are formed on semiconductor substrate for contacting to external leads directly therewith by simultaneous thermo-compression bonding, thereby dispensing with one-by-one bonding of fine gold wires. The metal bumps are generally formed by plating on metal layers which are formed on electrode pads formed on specified parts of the substrate. Conventional method of forming the metal bumps has shortcoming that bonding force of the bumps on the substrate is not sufficient, because an etchant used in the process likely etches the electrode pads.
FIG. 1(a), FIG. 1(b) and FIG. 1(c) show steps of such conventional method. The conventional method is elucidated in detail referring to FIG. 1(a) to FIG. 1(c). First, electrode pads 2 of aluminum film are formed on specified parts of the principal face of the silicon substrate 1 to connect it and lead out. On all the way of the principal face, an insulating film 3 of, for example, SiO.sub.2 is formed by known chemical vapor deposition method, and then, openings 31 are formed by means of known photo-etching method in a manner to expose almost area of the electrode pads 2, but retaining peripheral parts of the electrode pads 2 covered under the insulating film 3.
Next, by means of sputtering method or vacuum deposition method, for example, resistor heating method or electron-beam method, metal double layers 4' and 4" are formed on all the way of the principal face. The metal layers 4' and 4" are called barrier metals and are formed of two layers, a lower layer 4' and an upper layer 4" as shown in FIG. 1(a). The lower layer 4' is formed with such a metal that can make a strong contact with the electrode pads 2 of aluminum film and the chemical-vapor deposited insulating film 3 of such as SiO.sub.2. For example, chromium or titanium is suitable for the lower layer 4'. The upper layer 4" is formed with such a metal on that a metal bump 5 can be firmly formed in the subsequent step. For example, copper, nickel, gold, silver, platinum or/and lead are suitable for the upper layer 4".
Then, a photoresist film 6 is formed on all the way of the double metal layers 4' and 4", and openings 61 are formed by known photolithographic method so as to have the area corresponding to that of the electrode pad 2 thereby exposing the upper layer 4" therethrough. Thereafter, metal bumps 5 of thick metal layer is formed as shown in FIG. 1(b) by known electrolytic plating on the exposed area of the upper layer 4" by utilizing the exposed double metal layer 4' & 4" as electrode. Gold is suitable for the material of the metal bumps.
Then, the photoresist film 6 is removed by using known photoresist stripper, and subsequently, parts of the double layers 4' and 4" which are not covered by the metal bumps 5 are etched away by utilizing the metal bumps 5 as etching masks as shown in FIG. 1(c).
Inventors found that the abovementioned conventional method of making the metal bump has the following shortcomings that:
(1) The gold bumps 5 are utilized as etching masks in chemical etching to remove the metal double layers 4' and 4". In the etching, strong etchant comprising mixture of pottasium ferricyanide and sodium hydroxide or ferric chloride is used, and therefore, undesirable undercuttings of the metal double layers 4' and 4" occurs, thereby etching the double layers under the gold bump by the extent of etching width x. Sometimes the etching width reaches 5-10 .mu.m inward from the peripheral of the metal bump 5, and sometimes dissolves parts of electrode pad so as to make hollow 9 as shown in FIG. 1(c). Such undesirable dissolving causes electrical failure as well as decrease of contacting power of the metal bumps 5.
(2) The abovementioned shortcoming can be overcome when the openings (for electrolytic plating) in the photoresist film 6 is made larger than those of the openings in the SiO.sub.2 film 3 by the extent of the undercutting width x. However, such measure necessarily increases the width of the metal bumps 5, as well as increases pitches of the metal bumps. This leads undesirable increase of the size of IC or LSI wherein many lead wires must be integrated within a limited area.
In order to improve the abovementioned shortcomings, the inventors made preliminary improvements as shown in FIG. 2 and FIG. 3. These improvements are not yet disclosed to the public, and hence do not form the state of the art, but are described here for better understanding of the object and are only preliminary steps to the present invention.
In the inventors' preliminary improvement of FIG. 2, the feature is to make the area of the metal double layers 14' and 14" larger than that of the area of the metal bump 5, thereby to prevent the undercutting.
First, electrode pads 12 of aluminum film are formed on specified parts of the principal face of the silicon substrate 11 to connect it and lead out. On all the way of the principal face, an insulating film 13 is formed by known chemical vapor deposition method, and then, openings 131 are formed by means of known photo-etching method in a manner to expose almost area of the aluminum electrode pad 12, but retaining peripheral parts of the electrode pads 12 covered under the insulating film 13.
Next, by means of sputtering method or vacuum deposition method, for example, resistor heating method or electron-beam method, metal double layers 14' and 14" are formed on all the way of the principal face. The metal layers 14' and 14" are called barrier metals and are formed of two layers, a lower layer 14' and an upper layer 14" as shown in FIG. 2(a). The lower layer 14' is formed with such a metal, that can make a strong contact with the electrode pads 2 of aluminum film and the chemical-vapor deposited insulating film 13 of such as SiO.sub.2. For example, chromium or titanium is suitable for the lower layer 14'. The upper layer 14" is formed with such a metal on that a metal bump 5 can be firmly formed in the subsequent step. For example, copper, nickel, gold, silver, platinum or/and lead are suitable for the upper layer 14".
Then, a photoresist films 15 are formed on the upper layer 14" in a manner to have the areas which are a little wider than the areas of the electrode pads 12. Subsequently, the exposed areas of the upper layer 14", namely the parts of the upper layer 14" which are not covered by the photoresist films 15, are removed by a chemical etching by utilizing the photoresist films 15 as etching masks as shown in FIG. 2(b). The lower layer 14' is retained all the way of the principal face for the sake of later use as electric conductor in the step of electrolytic plating of the metal bumps. The retained lower layer 14' is used for forming the metal bumps on the regions of P-type conductivity formed in the semiconductor substrate of the N-type conductivity.
Then, the first photoresist film 15 is removed by known photoresist stripper, and subsequently, a second photoresist film 16 is formed by known photolithographic method in a manner to have openings 161 which are substantially over the area of the electrode pads 12. Thereafter, by utilizing the exposed parts of the lower metal layer 14' as electric conductor, a metal suitable for metal bump, such as gold, is plated by electrolytic plating method by utilizing the lower metal layer 14' as electric conductor and the exposed part of the upper metal layer 14" as electrode, so that the gold bumps 17 are formed on the exposed area of the upper layer 14" as shown in FIG. 2(c).
Next, the second photoresist film 16 is removed by known method, and subsequently, the lower metal layer 14' of the part which is not covered by the upper metal layer 14" is removed by known selective etching method by utilizing the upper metal layer 14" as the etching mask, thus completing the bump construction as shown in FIG. 2(d).
The method of FIG. 2 still has the following drawbacks:
(1) By using the upper metal layer 14" as the etching mask in the final stage, the upper metal layer is also etched to some extent, and therefore, the etchant infiltrates into the double metal layer from the peripheral part 18 of the interface between the metal bump 17 and the upper metal layer 14", into the aluminum electrode pad 12. Therefore, the infiltration of the etchant undesirably etches peripheral parts of the electrode pad 12, thereby producing electrical unstability of the device.
(2) For the upper metal layer 14" copper layer is suitable for obtaining strong mechanical contacting force with the overlying plated layer. The copper layer 14" is likely to form oxide film thereon in the subsequent steps. The first photoresist film 15 is processed with post-baking at 140.degree. C. to 200.degree. C. in order to strengthen adhesive force on the upper metal layer 14". Such post-baking is generally used when such photoresist film is used as etching mask for etching oxide-covered copper layer 14". As a result of the post-baking the photoresist film becomes very strong, and hence, removing of it requires immersing it for 5 to 10 minutes in 90.degree. C. to 100.degree. C. hot very strong solvent (mainly consisting of surface actant) called J-100. Such strong solvent at such high temperature undesirably etches the upper metal layer 14" with such a high etching speed of 500.degree. A per 6 minutes. Furthermore, the surface of the upper metal layer 14" is contaminated by the solvent, and therefore adhesive power between the metal bump 17 and the copper layer 14" is decreased and/or yield of forming the metal bump 17 becomes very poor.
(3) When a region 11' of P-type conductivity is formed as shown in FIG. 3 in an substrate 11 of N-type conductivity, and a metal bump 17' is formed on the P-type region 11', then it is necessary to use the lower metal layer 14' as electric conductor for the electrolytic plating. Namely, in FIG. 3, in order to form the metal bump by electrolytic plating method, the substrate 11 must be connected to the negative terminal B of a D.C. power source. In FIG. 3 parts corresponding to those of FIG. 2(d) are designated by corresponding numerals, and 12' and 13' designate electrode pad and insulating layer, respectively. When the substrate 11 is connected to the negative terminal, then a plating current can flow through the metal double layers 14' and 14" formed on the N-type region 11 of the substrate to the substrate 11, but another current from the metal double layer 14' and 14" formed on the P-type region 11', through the P-type region 11', to the N-type substrate 11 hardly flows, since the P-type region 11' and the N-type substrate 11 form a P-N junction of the reverse direction to the current. Therefore, forming of metal bump 17' on the P-type region is not possible. Therefore, it can be considered to use the lower metal layer 14' as electric path for the electrolytic plating to be connected a negative terminal A of a D.C. power source. But the lower metal layer 14' is made with chromium or titanium, in order to serve as barrier layer against diffusion of the overlying cupper and gold into the electrode pad 12' and further into the semiconductor substrate 11 or into the N-type region 11', and such metal as chromium or titanium has high resistivity for the electric path for plating. Therefore, the metal bump 17' formed on the P-type region 11' has smaller height (thickness) than other bumps 17 formed on the N-type substrate 11. Such non-uniform heights of the bumps causes unreliable contactings in the subsequent press-bonding to the external lead wires.
The specific resistivity of the vapor-deposited chromium film 14' changes responding with speed of vapor-deposition and thickness of the film 14'. For example, a 1,000 A thick chromium film made with the speed of 1A per second has 10.sup.-2 .OMEGA.cm resistivity, the same made with the speed of 2A per second has 10.sup.-3 .OMEGA.cm and the same made with the speed of 5A per second has 8.times.10.sup.-4 .OMEGA.cm. According to our experiment, the same chromium film made with the speed of 2.2-2.9A per second shows the resistivity of 1.7.times.10.sup.-3 .OMEGA.cm.
In FIG. 3, provided that the distance of the part where chromium layer 14' is exposed between the first metal bump 17 and the second metal bump 17' is 0.4 mm, the width is 50 mm and the thickness is 1,000A, then the resistance of the chromium layer of this part is 1.7.OMEGA., and when the distance is 1.2 mm the resistance of the same part is 5.1.OMEGA.. When the metal bumps 17 and 17' of gold are formed by electrolytic plating, provided that the plating is made with the current density of 0.035 mA/mm.sup.2, then on the double metal layers on the electrode pad 12 on the N-type substrate 11 the plating is made with the current density of 0.035 mA/mm.sup.2. But, on the double metal layers on the electrode pad 12 on the P-type region 11' the plating is made with the current density of 0.029 mA/mm.sup.2 for the abovementioned distance of 0.4 mm and 0.023 mA/mm.sup.2 for the distance of 1.2 mm. As a result of calculation, the plating speed on the N-type substrate 11 is 11.2 .mu.m/hour for the above-mentioned current density of 0.035 mA/mm.sup.2, while the plating speed on the P-type region 11' is 9.2 .mu.m/hour for the current density of 0.029 mA/mm.sup.2 and 7 .mu. m/hour for the current density of 0.023 mA/mm.sup.2. Thus, due to the non-uniformity of the plating speed, the height of the metal bump differs as shown in FIG. 3. Furthermore, because the chromium layer 14' has the high resistivity, only on the parts which are close to the part connected to the negative terminal B the metal bump becomes tall while they are lower in more apart parts.